The present invention relates to memory bus architecture, and in particular to a memory bus capable of interfacing to memory modules which hold a multiplicity of different types of memory devices.
Many types of memory exist in a modem computer system including static RAM, dynamic RAM, programmable FLASH, and magnetic disks. Over the years the physical locations of these memories have become separated due to various electrical and physical differences between the memory types. Helped by the increasing miniaturization of memories, it is now become possible to combine these memories on a few subassemblies or modules.
However, due to a number of factors, previous attempts at producing memory modules which incorporate different types of memory on the same module have failed to find widespread acceptance. It is the purpose of this invention to describe the necessary characteristics of a universal memory bus that allows properly constituted memory modules to incorporate a wide variety of memory types. the 1960""s, DRAM memory modules were introduced by Wang Computer and subsequently by many other manufacturers. Many benefits resulted from placing multiple DRAM memory chips on a removable memory module instead of directly on the same printed circuit board (PCB) as the CPU. These include saving space on the CPU board, efficiency of manufacturing and testing, and allowing the user of the computer system to easily upgrade the amount of DRAM memory in his system.
Because of the benefits just described, DRAM memory modules are now the standard means by which DRAM is included in a computer system. Also, because it is recognized that other types of memory besides DRAM memory can benefit from placement on similar modules, memory module standards can include specifications for other types of memory. The standards for the most common memory modules are done by an international committee called JEDEC and are defined in JEDEC JESD 21 C Solid State Memory Standards. The following discussion looks at a specific JEDEC 100 pin DIMM Standard (JEDEC Standard No.21-C 4.4.8) in order to illustrate one means by which different types of memory can be placed in the same physical form factor.
The JEDEC 100 pin DIMM standard has assigned pins for three types of memory devices; namely DRAM, SDRAM, and ROM. FIG. 1 of this patent illustrates how two 100 pin DIMM modules 14 and 16 with different memory types can be placed in the same computer system 10. The connection scheme for the two 100 pin DIMM modules 14 and 16 shown in FIG. 1 avoids signal conflicts between different types of memory by restricting each individual module 14 and 16 to only one type of memory device per memory module.
However, it is desirable to allow a memory bus to be connected to a suitable memory module that contains a variety of types of memory devices. The desired memory bus 12xe2x80x2 and module 18 are shown in FIG. 2. To understand the problems associated with the memory module scheme of FIG. 2, three new terms will be introduced; namely, xe2x80x9cmemory elementxe2x80x9d, xe2x80x9cmemory use modexe2x80x9d, and xe2x80x9cmemory signal setxe2x80x9d. The term xe2x80x9cmemory elementxe2x80x9d refers to either a memory chip or memory module. The definition of the terms xe2x80x9cmemory use modexe2x80x9d and xe2x80x9cmemory signal setxe2x80x9d will be made clear in the subsequent paragraphs.
All the signals of a memory element can be divided in four signal groups; power, control, address, and data. The power lines provide the energy for the chip to function. The address lines are used to access a specific location of memory. The data lines provide the information at the addressed locations. And the control lines provide the direction and control of the data transfer.
Now comes the central question with respect to producing a workable memory module with multiple types of memory. If we include a complete set of power, control, address, and data signals in the connector of our universal memory element, would we not have a working multi-memory element?
End The answer to the above question is no; because the signal definition for any given pin on a memory element can be different depending the actual memory use mode of the memory element.
An example of more than one use for a particular memory pin is described herein below. Parallel EPROM/FLASH memories typically hold the boot code for standard Personal Computers. These memories are used because they retain their programmed data when powered down yet provided fairly fast access to this same data when powered up. The signals of a parallel EPROM/FLASH memory include an address line described as A9. When such a memory is normally used in a computer system, the address line A9 is wired like all the other address lines of the device and is connected to line A9 of the local CPU 102 bus. FIG. 3A illustrates the connection of the address line A9 to line A9 of the CPU 102.
However, when the EPROM/FLASH is programmed with the boot code for the CPU, by convention, a special super voltage is placed on A9 along with other suitable signals in order to allow a PROM programmer (a test instrument) to identify the actual type of EPROM being programmed. FIG. 3B illustrates the connection of the address line A9 of the EPROM/FLASH device 104 to a super voltage. The identification number read is usually a four byte hexadecimal number and is called the device""s silicon signature. Thus we see that the signal definition of A9 for the typical boot EPROM/FLASH device 104 depends upon whether the chip is in the programming mode or in the normal memory access mode.
When both the EPROM/FLASH device 104 and a non-programmable memory such as a DRAM are placed on the same memory card, a programming problem will occur. Namely, if A9 of the programmable memory is connected to A9 of the DRAM, we will not be able to place a super voltage on A9 to read the silicon signature of the EPROM/Flash us memory because it will harm the DRAM. If on the other hand, we keep them separate, the two different memory devices will not share the same signals on the memory bus.
Other common parallel EPROM and FLASH signals lines which often have super voltage values (e.g. 12 volts) applied during the programming mode include the memory chip select, output enable, write enable, and the reset/power down lines. For EPROM""s, these super voltages often need to be applied for programming of the main memory array. In FLASH devices, these signals are typically needed to program special sections of the device for protection of sectors from regular programming which are commonly referred to as xe2x80x9cboot block sectorsxe2x80x9d.
All of the groups of signals required for the various modes of programming form a group of xe2x80x9cprogramming signal setsxe2x80x9d for the xe2x80x9cprogram use modexe2x80x9d. An accommodation for many of the super voltages required for the programming signal sets is typically absent from current memory module design. Only the intended memory use mode of the memory device is considered when selecting the actual signals that constitute the signal lines of the memory module. This is precisely the case with the JEDEC 100 pin DIMM standard reviewed earlier.
When all of the memory devices on a memory module are of the same device type, this will normally not present a problem in terms of programming. However, in the case of a Ids mixed memory type module, the inability to connect the correct programming signal sets will prevent full testing and programming of the programmable device on a module.
It is important to note that all memory elements including non-programmable memory elements have at least two different memory use modes; namely, a group of test modes and also the normal intended memory read and write access modes. These latter as modes will be referred to as the xe2x80x9cnormal use modesxe2x80x9d. Since the signal sets required for testing non-programmable devices may also conflict with the signal sets required for the normal use mode, the mixing of different types of memory on any give module may present real conflicts due to differences in the test modes between each type.
In addition, every programmable memory element has at least three different memory use modes; namely test mode(s), programming mode(s), and normal use mode(s). Typically, the memory manufacturer will be concerned with all three modes. The PROM programmer manufacturer will normally be concerned with only the programming mode(s). The user of the memory element will be concerned with at least the normal use mode(s) and sometimes with the programming mode(s) if in circuit programming is desired.
To simplify the discussion of these memory element use modes, the term xe2x80x9csignal setxe2x80x9d will now be defined. A signal set is a group of signals that are required on a memory element for performing an operation in a valid memory element use mode. Typical signal sets for a programmable memory element include the following types of signal sets; test sets, programming sets, info sets, and normal use mode sets.
The general definitions for these signal set categories are self explanatory with the possible exception of the info set. The info set refers to the collection of signals commonly found on a memory element which allow the CPU to access specific module and signal information about the element. Common synchronous dynamic memory (SDRAM) DIMM modules include a special EEPROM serial device referred to as the xe2x80x9cserial presence detectxe2x80x9d device (SPD device) which include a data base of information about the characteristics of the SDRAM on the module memory. The signal set used to get this information from the SPD device constitutes an info set.
In the case of a programmable memory device supporting silicon signatures, the set of signals required to read the device silicon signature function belong to an info signal set in the programming use mode. Another example of an info signal set in the normal use mode is the signals on the PCMCIA connector which allow reading the card information structure (CIS) data base of a PCMCIA card.
As has been discussed, standard JEDEC memory modules do not contain multiple types of memory devices. However, there is another standard type of memory module or card that is capable of satisfying this requirement and that is one designed to the PCMCIA (or PC-Card) standard.
The original PCMCIA or (PC-Card) bus is a 68 pin bus which allows for different types of memory to reside on one module (4). Although designed originally for non-multiplexed 8 bit and 16 bit data buses, the newer Card Bus standard allows for a multiplexed 32 address/data bus. The following remarks refer to the older standard (PCMCIA 2.1/JEIDA 4.2) but apply equally well to the newer 32 bit bus standard.
The signals of the PCMCIA define three xe2x80x9cmemory spacesxe2x80x9d. By xe2x80x9cmemory spacexe2x80x9d we mean a decoded memory region. These three regions are shown in FIG. 4 and are commonly referred to as the Common Memory area 204, the Attribute Memory area 202 or (CIS area), and the I/O area 206. Selection of either the Common Memory area 204 or CIS area 206 is performed with the Reg# line (pin 61). If during a memory access where OE#(pin 9) or WE# (pin 15) are asserted and the #Reg line is low, the CIS memory area 202 is selected. Alternatively, when #Reg is high, the Common Memory area 204 is selected. Selection of the I/O area 206 is performed by choice of a different Read/Write signal pair; namely IOWR# (pin 44) or IOWR# (pin 45). With regard to programmable devices, the PCMCIA bus has two VPP or super voltage lines.
The Attribute Memory area 202 is included on the PCMCIA bus to allow the system CPU accessing the PCMCIA card to obtain information on the intended purpose of the card such as Fax/Modem, Ethernet, solid state disk (ATA card), or linear SRAM or Flash card. The information is stored on the card in a data base structure called the Card Information Structure (CIS). Similar to the SPD device on SDRAM modules described earlier, the CIS device shares restricted status with the main memory devices that are normally found in the Common Memory area 204. However, because both the CIS memory area 202 and the Common Memory area 204 share the same address and control pins (except for the #Reg line), a PCMCIA Linear or ATA memory card is a good example of a module with multiple types memory residing on the same card.
The PCMCIA 200 bus has two main limitations as a multiple memory bus. First, it lacks many of the common signals required by modem DRAM memory such as the. multiplexed address strobe signals RAS and CAS and no apparent way to add these signals. Secondly, although there are two VPP super voltage lines which can be used to program common programmable memory chips such as EPROM and Flash memory, the PCMCIA bus has no provision for taking care of super voltages used on such lines as the output enable line or address line A9.
Rephrasing the last statement in terms of the concept of signal sets, the PCMCIA does not provide any direct means by which the use of multiple signal sets can be applied to different types of memory devices on a PCMCIA card.
Michelson in U.S. Pat. No. 5,628,028 presents a way around these limitations of the PCMCIA bus. This is shown in FIGS. 5A and 5B. The Michelson solution is to include a field programmable gate array (FPGA) on the PCMCIA card. This addition along with an appropriate program on the host computer allows for a wide variety of memory operations on the PCMCIA card. A short synopsis of the Michelson method is as follows.
1. The CIS region is read by the host computer which then knows that a PCMCIA card is available that requires its FPGA to be loaded through the PCMCIA bus.
2. The FPGA is loaded with correct data which modifies how the common memory region will respond to memory requests.
As shown in FIG. 5A, the FPGA 302 is now a memory controller which, for example, can change the asynchronous, non-multiplexed common memory space of the PCMCIA bus into a synchronous, multiplexed address bus of SDRAM memory 304. Also as shown in FIG. 5B, the FPGA 302 can act as converter of signal sets so that both a PROM programming signal set and a normal mode signal set can be accessed through the same PCMCIA bus signals.
The PCMCIA bus standard along with the FPGA arrangement disclosed in Michelson is indeed a solution to how multiple types of memory can coexist on the same memory module. Unfortunately, the requirement that the memory card incorporate an FPGA which must act as a memory controller means that the high speed signal requirements of many fast synchronous SDRAM memories will be difficult if not impossible to meet. Secondly, the restriction that the host computer must access the CIS region and load the FPGA with the appropriate code adds complexity to its use. Thirdly, the requirement of adding the hardware to the PCMCIA card as well as the storing and loading the appropriate FPGA code to allow different signal sets to be applied to the PCMCIA bus for performing typical programmable memory programming tasks is also a difficult and expensive task.
For the reasons stated above, commercial PCMCIA cards are largely restricted to signal memory type usage, do not support DRAM devices, and fail to allow programming of Flash devices except in programming modes that do not require super voltages on pins such as OE, WE, or A9.
Accordingly, what is needed is a system and method for allowing a variety of memory devices to be utilized as one memory module. The method and system should be easily implemented, cost effective and compatible with existing memory bus architectures. The present invention addresses such a need.
A memory card in accordance with the present invention allows a variety of memory devices to interface with a processor. The. memory card comprises a data base which contains information about the variety of memory devices that are on the card and dual signal pairs that can be used to form different signal sets that are required to test or program the variety of memory devices. The memory card further comprises a plurality of reserved lines that can be used to form additional signal sets and a plurality of memory areas.
A memory card in accordance with the preseat invention comprises four different signal groups which allows memory modules that individually contain multiple memory types to be interfaced to a standard CPU. Such a memory bus is referred to as an X-Bus and the memory modules are referred to as X-Cards. The four signal groups of the X-Bus/X-Card combination are described below.
1. The X-Bus has a plurality of signals that connect to a device on the X-Card that contains information on all devices that exist on the X-Card. This device is referred to as the XDD (the X-Card Database Device).
2. The X-Bus also contains dual signal pairs that can be used to form different signal sets. These signal sets are required to test and or program typical memory devices such as FLASH programmable devices.
3. The X-Bus also provides a multiplicity of defined signals required to normally access most common memory types. One of these defined signals is a chip select signal (preferably #CS0), which is normally used to boot a computer system from reset.
4. Further, the X-Bus provides a multiplicity of reserved lines that can be used to form the different signal sets required for the testing, programming, and/or normal use modes of standard memory devices.